1. Field of Invention
The present invention relates to a high speed interface type semiconductor memory device, and in particular to an improved high speed interface type semiconductor memory device which can transmit data of a plurality of DRAMs of a module to a controller by using only one data strobe clock signal.
2. General Background and Related Art
In general, through a read path, a signal amplified by a sense amp in a row address path is applied from a bit line to a data bus line according to selection of a column selector, re-amplified by a data bus line sense amp, and inputted to an output buffer. Through a write path, a data inputted from a data input buffer is applied to a sense amp. The read and write paths are called a data path.
A plurality of DRAMs are connected on one module in a system bus structure of a conventional semiconductor memory device. The DRAMs are controlled by a controller through a signal bus line.
The DRAMs connected to the signal bus line are controlled by one controller, and thus have a different phase difference in order to recognize a data and a control signal from the controller in an identical time. That is, the DRAM far from the controller rapidly processes the data, and the DRAM adjacent to the controller slowly processes the data.
The DRAMs controlled on the module by the controller are located in a different position. Thus, data strobe signals as many as the DRAMs are required to overcome skew of data from the respective DRAMs. The data output from the DRAMs during the read operation are synchronized with the data strobe signals, and transmitted to the controller.
In the conventional semiconductor memory device, the data strobe signals as many as the DRAMs are required to transmit the output data from the DRAMs to the controller. As a result, the conventional semiconductor memory device requires as many bus lines as there are data strobe signals, thereby occupying a large circuit area.
The claimed inventions feature at least in part a high speed interface type semiconductor memory device which can transmit data of a plurality of DRAMs of a module to a controller by using one data strobe clock signal.
There is provided a high speed interface type semiconductor memory device including a DRAM module unit for generating a strobe clock signal for synchronizing a data signal in a read operation in a DRAM farthest from a controller among a plurality of DRAMs, providing the strobe clock signal to the other DRAMs, and transmitting data to the controller during the read operation. A controller transmits a clock signal and data signals synchronized with the clock signal to the plurality of DRAMs, and receives data signals from the DRAMs.
Each DRAM includes a first buffer for receiving main clock and clock bar signals from the controller. A second buffer buffers a first internal clock signal obtained by delay locking the main clock signal according to a control signal, and outputs data strobe clock and clock bar signals. A third buffer buffers and outputs the data strobe clock and clock bar signals according to the control signal. A DLL unit receives the output signal from the first buffer and the output signal from the third buffer, and outputs the first internal clock and clock bar signals, second internal clock and clock bar signals obtained by 90xc2x0 phase-shifting the first internal clock and clock bar signals, third internal clock and clock bar signals, and fourth internal clock and clock bar signals obtained by 90xc2x0 phase-shifting the third internal clock and clock bar signals. A first multiplexer unit selectively transmits the first internal clock and clock bar signals or the third internal clock and clock bar signals according to the control signal. A second multiplexer unit selectively transmits the second internal clock and clock bar signals or the fourth internal clock and clock bar signals according to the control signal. A read first-in first-out unit synchronizes and outputs a 4 bit read data according to the output signals from the first and second multiplexer units. A fourth buffer is connected between the read first-in first-out unit and a DQ pad. A fifth buffer receives a write data inputted through the DQ pad. A write first-in first-out unit receives the output signal from the fifth buffer, synchronizing the output signal according to the first internal clock and clock bar signals and the second internal clock and clock bar signals, and outputs a 4 bit write data. The first internal clock and clock bar signals and the third internal clock and clock bar signals are delay locked signals by the DLL unit receiving the main clock and clock bar signals.